In a full system simulation, the full hardware platform (e.g., processor cores, devices, buses, memory) of a computer system is simulated. Processor cores are often simulated by an ISS (Instruction Set Simulator). These cores are used to execute the embedded software of the simulated platform.
When the embedded software wants to access the devices and memory in the simulated system, it issues load and store instructions. The processor core then retrieves or changes the data by putting a request on a bus. In contemporary cores, caches and memory management units (MMUs) make this process more complex—before the request is put on the bus, the core translates the virtual address into a physical address, checks to see if the physical address resides in cache or not, and also checks permissions. Table 1 below shows an example path for a load.
TABLE 1Example path for a loadLoad -> check permissions -> translate to physical address ->check cache -> transfer over the bus -> do the load
Thus, simulating a device or memory access requires multiple checks and execution of a relatively large amount of code before a real access to a device or memory can be performed. Various techniques are employed to make simulation of this process faster. These techniques include the use of Transaction Level Modeling (TLM) to simulate the bus to make bus accesses faster, the use of an abstract (but less accurate) model of the processor cache, and/or the use of an extra simulation cache to map a virtual address to a physical address.
Table 2 describes an example of a memory path that is followed before the content of memory is found.
TABLE 2Example memory path implementation--unsigned long read32(virtual_address){ if(cache_virtual->contain(virtual_address)) {  return cache_virtual->read32(virtual_address); } physical_address =translate_virtual_to_physical(virtual_address); if(cache_physical->contain(physical_address)) {  fill_virtual_cache_when_needed( . . . );  return cache_physical->read32(physical_address); } if(cachable(virtual_address, physical_address) {  returnfill_virtual_and_or_physical_caches_if_needed(virtual_address,physical_address, . . . ); } else {  device = lookup_device(physical_address);  return device->read32(physical_address); }}--
Depending on how the processor is simulated, “cache_virtual” and/or “cache_physical” may or may not be available. The implementation of “device→read32” may pass through another (e.g., second level) cache that is outside the simulated processor. However, even when no processor cache is simulated and TLM is used to simulate the bus, a lot of processing time may still be consumed.